Reports
Floor Plan Analysis
This provides for a report which includes an annotated die photograph with identified functional blocks. A table detailing the relative dimension of the blocks as well as the overall percentage the block types occupy on the die are also provided. The functional blocks are identified based on experience, available public documents, and other factors regarding the use of the chip.
Circuit Analysis
This provides for a report which includes a set of functional schematics organized in a hierarchical manner based on topographical layer images of an integrated circuit. Schematics are entered using an EDA (Electronic Design Automation) with active and passive devices properly instantiated. Pinouts are also appropriately labeled. The hierarchical organization and grouping are also closely matched to a functional block diagram if this background information is made available.
Process Analysis
This provides for a report which contains structural analysis information, in addition to a floorplan analysis of an integrated circuit. The structural analysis would include pitch dimension measurements of metal routing as well as cross-sectional analysis. Materials analysis (SEM-EDS) provides additional information on the cross-sectional layers that are needed to identify the materials making up the layers.